1. Field of the Invention
The present invention relates to a semiconductor device, more particularly an MOS (metal oxide semiconductor) type device, as well as the process for producing to a same.
2. Description of the Prior Art
The conventional MOS type device comprises a P (or N) type semiconductor substrate, with N(P) type semiconductor regions on the substrate and an oxide layer placed on a part of the P(N) type semiconductor substrate. An N(P) type semiconductor region is established under the oxide layer by inversion and is used for a channel region. By placing suitable materials for electrodes on exposed parts of the N(P) type semiconductor regions, one of these regions is used for a source region and the other region is used for a drain region.
According to a recently developed MOS type field effect transistor with an aluminum gate, an insulating layer is buried under the semiconductor layer below the source and drain regions (IEEE TRANSACTION OF ELECTRON DEVICES, OCTOBER, 1976, pages 1190 and 1191). This buried insulating layer, which is formed by thermal oxidation of the silicon substrate, is located usually below the entire semiconductor layer except for the channel region of the transistor, and in the proximity of the channel region. The transistor with such a buried insulating layer has an excellent high frequency property. This is because the junction capacitance between the P(N) type semiconductor substrate and the N(P) type semiconductor layer of the source and drain regions is reduced because the N(P) type semiconductor layers are placed on the insulating layer.
It is known from the published Japanese Patent Specification No. 50-13154 and from U.S. Pat. No. 3,600,651 that the buried insulating layer is placed on the entire silicon substrate except for a channel region of the MOS type field effect transistor. Since the source and drain regions and their surrounding portions are formed entirely on the buried insulating layer, the junction capacitance is reduced further than it would be by the MOS type field effect transistor known from the publication mentioned above.
The structure of the MOS type field effect transistor having a buried insulating layer will now be illustrated in detail with reference to FIGS. 1(a), (b) and (c).
Referring to FIG. 1 showing a cross sectional view of the MOS type field effect transistor, the insulating layer 2 consisting of silicon dioxide is formed on the P(N) type semiconductor substrate 1 and has a window to expose a part of the substrate, on which part the single-crystalline epitaxial silicon layer 3 is placed. This silicon layer 3 is provided with a P.sup.- (N.sup.-, the minus sign indicating low conductivity) conductivity when epitaxially grown on the P(N) type silicon substrate 1. The the silicon layer 3 is first deposited on the entire top surface of both the exposed substrate 1 and the silicon dioxide layer 2, but a peripheral part of the deposited silicon becomes polycrystalline. This part is shown in FIGS. 1(a) and (b) as a part of the polycrystalline silicon layer 4a and 4b, which is deposited on the silicon dioxide layer 2. The polycrystalline silicon of the layer 4a and 4b is doped with the N(P) type impurity and has N.sup.+ (P.sup.+, the plus sign indicating high conductivity) type conductivity. A circumferential part of the single-crystalline silicon layer 3 is changed to N(P) type conductivity by the N(P) type impurity of the polycrystalline silicon layer 4a and 4b, and therefore, is numbered as 3b and 3c so as to distinguish it from the original P(N) type layer 3a. Exposed parts of the silicon substrate 1 are also changed to N(P) type conductivity, and therefore, are denoted as 1b and 1c, so as to distinguish them from the silicon substrate 1a having the original P(N) conductivity. The silicon dioxide layer 5, surrounds the polycrystalline silicon layer 4. The P(N) type polycrystalline silicon layer 6 of a gate is formed on the thin insulating film 7 comprising for example, silicon dioxide, which is formed on the single-crystalline silicon layer 3. The PSG (phosphosilicate glass) layer 8 having windows covers the entire surface of the MOS transistor and metallic electrodes 9 and 10 are brought into ohmic contact with the polycrystalline silicon layers 4a and 4b, respectively, through the windows.
The source region is established in the polycrystalline silicon layer 4a, single-crystalline silicon layer 3b and the silicon substrate 1b. Similarly, the channel region is established in the top part of the P(N) type silicon layer 3a. The drain region is established in the polycrystalline silicon layer 4b, single-crystalline silicon layer 3c and the silicon substrate 1c. Since the polycrystalline silicon layers 4a and 4b are separated from the substrate 1 by the silicon dioxide layer 2, the junction capacitance mentioned above is very much reduced.
The planar relationship between each of the source, channel and drain regions will be apparent from FIG. 1(c). The rectangular area surrounded by the line L.sub.4a corresponds to the exposed part of the polycrystalline silicon layer 4a. The metal wire 9 extends over the top of the transistor. The area surrounded by the solid line L.sub.s corresponds to the source region, which is established in the N(P) type silicon layers 4a and 3b. The rectangular area surrounded by the line L.sub.4b corresponds to the exposed part of the polycrystalline silicon layer 4b. The metal wire 10 extends from the exposed area of the silicon layer 4b. The area surrounded by the solid line L.sub.d corresponds to the drain region, which is established in the N(P) type silicon layers 4b and 3c. The area surrounded by the line L.sub.G corresponds to the limits of the polycrystalline silicon gate electrode 6, which is exposed at the area surrounded by the line L.sub.6. The metal wire 11 extends from the exposed area of the silicon gate electrode 6, surrounded by the line L.sub.6. The channel region established below the silicon dioxide film 7 is indicated in FIG. 1(c) by all the broadly spaced diagonal lines. The source region (L.sub.s), the channel region and the drain region (L.sub.d) are, therefore, successively connected. The metal wires 9, 10 and 11 electrically connect the source and drain regions, and the silicon gate electrode respectively.
A disadvantage of the known MOS type transistor having the buried silicon dioxide layer 2 will be apparent from FIG. 1(b), which is a cross sectional view of FIG. 1(a) along the line (b)--(b) in FIG. 1(c). The channel region is established in the P(N) type single-crystalline silicon layer 3a having a trapezoidal cross section. The width of the bottom of the trapezoidal silicon layer 3a is equal to the width W.sub.ox of the window in the buried silicon dioxide layer 2. Parts of the silicon layers which are deposited on the exposed and oxidized part of the silicon substrate become polycrystalline, as denoted in FIG. 1(c) as 4d and 4e. It is to be noted that a part of the silicon deposited on the substrate 1 becomes single-crystalline layer 3a and the other part becomes polycrystalline, as explained with reference to FIG. 1(a). When the polycrystalline silicon layer, except for the layers 4a and 4b, is oxidized to the silicon dioxide layer 5, both the single-crystalline silicon layer 3a of the channel region and the polycrystalline silicon layers 4d, 4e are masked by the thin silicon dioxide layer 7 having a width W.sub.G. The polycrystalline silicon layers 4d and 4e are, therefore, left non-oxidized, as shown in FIG. 1(b).
Since the diffusion constant of an impurity in polycrystalline silicon is greater than in single-crystalline silicon, the impurities for doping into the source and drain regions L.sub.s and the L.sub.d, respectively, (FIG. 1 (c)) are rapidly diffused into the polycrystalline silicon layers 4d and 4e, which are shown with the narrowly spaced diagonally lines in FIG. 1 (c). The polycrystalline, doped silicon layers 4d and 4e extend through the MOS transistor, as shown in the narrowly hatched areas of FIG. 1(c), and the a short between the source region (L.sub.s) and the drain region (L.sub.d) occurs due to the polycrystalline silicon layers or passages 4d and 4e running therebetween. The production yield of the MOS type semiconductor device having the buried insulating layer is low.